Alliance Memory Launches New LPSRAMs With Embedded Error-Correction Code; 1Mb and 4Mb Devices Boost Reliability Over Previous Generation Devices

KIRKLAND, Wash. — Jan. 25, 2023 — Alliance Memory today announced that the company has expanded its portfolio of low power asynchronous SRAM (LPSRAM) products with new 1Mb and 4Mb devices that feature embedded error-correction code (ECC). Compared to previous generation devices, the new AS6CE1016A (1Mb) and AS6CE4016B (4Mb) offer better failure in time (FIT) and mean time to failure (MTTF) characteristics with reduced soft error rates (SER) for more reliable operation in a wide range of consumer, industrial, communications, and medical applications.

The new LPSRAMs’ ECC feature provides 1-bit error correction per byte, which makes them particularly suitable for low power applications and battery backup nonvolatile memory applications. Data retention voltage for both devices is 1.5V with typical data retention current of 1µA for the 1Mb AS6CE1016A and 2µA for the 4Mb AS6CE4016B. The devices operate from a single power supply of 2.7V to 3.6V, and all inputs and outputs are fully TTL compatible.

With their enhanced performance, the new LPSRAMs are designed to meet the demands of a very wide range of applications, such as routers and switches in communications systems; programmable logic controllers in industrial automation systems; printers, gaming machines, musical instruments, and calculators; vending machines and ATMs; and elevator systems, control panels, and fire control systems.

Key device specifications and package options are shown in the table below.

Device Specification Table:

Part number	Organization	VCC range	Access time	Operating temperature	Package
AS6CE4016B-45ZIN	256K x 16	2.7 – 3.6V	45 ns	-40 ~ 85°C	44-pin 400 mil TSOP II
AS6CE4016B-45BIN	256K x 16	2.7 – 3.6V	45 ns	-40 ~ 85°C	48-ball 6mm x 8mm FBGA
AS6CE1016A-45ZIN	64K x 16	2.7 – 3.6V	45 ns	-40 ~ 85°C	44-pin 400 mil TSOP II